The present device relates generally to data communications circuits and, in particular, to a universal asynchronous receiver/transmitter (UART) with improved data handling functionality for use with a various CPUs and peripherals.
Most digital circuits process data in parallel to provide more efficient processing. Many digital devices also use a serial port for bringing data to and from the device from a remote site, often coupled to a relay station via a telephone or LAN line. The universal asynchronous receiver/transmitter (UART) is such a digital device that performs parallel-to-serial conversion of digital data. A UART communicates between parallel and serial forms by converting received data between parallel I/O devices, such as a local CPU, and serial I/O devices, such as POTS modems, Ethernet devices and other communications devices. Most traditional UART devices can be programmed to operate at a selected baud rate, and newer generation UARTs handle communications more efficiently as technology advances, to a great extent due to larger FIFO depths and improved flow control (e.g., fewer retries required and waits for the internal FIFO to fill or empty).
UART devices typically operate in one of two software modes: either in a polled mode or in an interrupt mode. In the polled mode, software periodically monitors internal registers to determine if a read or a write action is necessary. In the interrupt mode, software waits for an interrupt event to trigger a read or a write to a particular register. Most of the software monitoring functions used in these applications involve receive and transmit FIFOs that contain serial communications port data. A trigger level for respective FIFOs is usually defined that indicates to the software that it is time to receive or transmit data. Unfortunately, latency time between reaching the trigger level and using the software to prompt the CPU to read or transmit the data in the FIFOs can be sufficiently high so as to lose data in the process.
Various aspects of the present invention are directed to facilitating efforts to improve CPU efficiency in controlling data flow through a FIFO circuit of a UART chip. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, is adapted to control the data flow through the FIFO circuit.
More particular implementations of the present invention entail using the CPU to control the data flow through a FIFO circuit, in response to varying levels of storage capacity in the FIFO circuit, by determining when to control the data flow through the FIFO circuit or determining immediately whether or not to control the data flow through the FIFO circuit. In another example implementation, the CPU adjusts a previously programmed parameter used to prompt a subsequent polling of the UART chip in response to the FIFO circuit storage capacity level.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.